research-article
Authors: Wenfa Zhan and Luping Zhang
Volume 96, Issue C
Published: 02 July 2024 Publication History
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Abstract
With the continuous shrinkage of integrated circuit feature sizes, circuit design has become increasingly complex, leading to issues such as rising test complexity and inefficiency. A dynamic adjustment method of test vectors for effective transistor critical area coverage based on the internal structure of the circuit is proposed. The test quality of the test vector is measured in terms of the transistor feature size relative to the size of the circuit unit. First, this method comprehensively considers the problem of circuit complexity. The test eigenvalue of each test vector is comprehensively calculated based on the overall test results. Then, the test vectors are sorted from the highest to the lowest test quality. Furthermore, during the testing process, the order of the test vectors is dynamically adjusted according to the eigenvalues of the test vectors. This method can significantly reduce the test time for failed integrated circuits. Experiments using ISCAS 89 and ITC 99 circuits show that the test process after reordering reduces the test time by 37.98% and 36.15%, respectively. Therefore, the test efficiency of the chip is improved and the test cost is optimized.
Highlights
•
This paper provides test cost reduction without increasing the defect level obviously.
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Test time and test quality have been greatly improved.
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This method shows superior effects on large-scale circuits; the larger the scale, the better the performance.
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A mathematical model of the internal structure of the transistor was developed to measure the quality of the test, making it applicable.
References
[1]
B. Hoefflinger, IRDS—International Roadmap for Devices and Systems, Rebooting Computing, Springer, Cham, 2020, pp. 9–17,. S3S[M]//NANO-CHIPS 2030.
[2]
M. Liu, K. Chakrabarty, Adaptive methods for machine learning-based testing of integrated circuits and boards[C]//2021 IEEE international test conference (ITC), IEEE (2021) 153–162,.
[3]
N. Agrawal, M.J. Yang, C. Xanthopoulos, et al., Automated socket anomaly detection through deep learning[C]//2020 IEEE international test conference (ITC), IEEE (2020) 1–5,.
[4]
A. Shafa*ghi, Equipment failure rate updating—Bayesian estimation, J. Hazard Mater. 159 (1) (2008) 87–91,.
[5]
K.R. Gotkhindikar, W.R. Daasch, K.M. Butler, et al., Die-level Adaptive Test: Real-Time Test Reordering and elimination[C]//2011 IEEE International Test Conference, IEEE, 2011, pp. 1–10,.
[6]
W. Zhan, Z. Shao, A graded dynamic adjustment method for integrated circuit test flow, J. Electron. 48 (8) (2020) 1623–1630,. (In Chinese).
[7]
T. Song, T. Ni, Z. Huang, et al., Valid test pattern identification for VLSI adaptive test, Integration 82 (2022) 1–6,.
Digital Library
[8]
F. Hapke, P. Maxwell, Total Critical Area Based testing[C]//2018 IEEE International Test Conference (ITC), IEEE, 2018, pp. 1–10,.
[9]
F. Hapke, W. Howell, P. Maxwell, et al., Defect-oriented test: effectiveness in high volume manuf-acturing, IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 40 (3) (2020) 584–597,.
[10]
G.Y. Lin, K.H. Tsai, J.L. Huang, et al., A Test-Application-Count Based Learning Technique for Test Time reduction[C]//VLSI Design, Automation and Test (VLSI-DAT), IEEE, 2015, pp. 1–4,.
[11]
Y. Li, E. Yilmaz, P. Sarson, et al., Online Information Utility Assessment for Per-Device Adaptive Test flow[C]//2018 IEEE 36th VLSI Test Symposium (VTS), IEEE, 2018, pp. 1–6,.
[12]
C. Xanthopoulos, D. Neethirajan, S. Boddikurapati, et al., Wafer-Level Adaptive Vmin Calibration Seed Forecasting[C]//2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019, pp. 1673–1678,.
[13]
V.A. Niranjan, D. Neethirajan, C. Xanthopoulos, et al., Trim time reduction in analog/RF ICs based on Inter-Trim correlation[C]//2021 IEEE 39th VLSI test Symposium (VTS), IEEE (2021) 1–7,.
[14]
M. Shintani, M. Inoue, T. Nakamura, et al., Wafer-level variation modeling for Multi-site RF IC testing via Hierarchical Gaussian process[C]//2021 IEEE International test Conference (ITC), IEEE (2021) 103–112,.
[15]
A. Shrivastava, G. Banerjee, Functional testing of on-chip analog/RF circuits using Machine learning based regression models[C]//2022 IEEE international test conference India (ITC India), IEEE (2022) 1–7,.
[16]
L. Wu, S. Rao, M. Taouil, et al., Testing STT-MRAM: manufacturing defects, fault models, and test solutions[C]//2021 IEEE International test Conference (ITC), IEEE (2021) 143–152,.
[17]
L. Wu, S. Rao, M. Taouil, et al., Defect and fault modeling framework for STT-MRAM testing, IEEE Transactions on Emerging Topics in Computing 9 (2) (2019) 707–723,.
[18]
B. Arslan, A. Orailoglu, Aggressive test cost reductions through continuous test effectiveness assessment, IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 35 (12) (2016) 2093–2103,.
Digital Library
[19]
Y. Zhang, Y. Ding, Z. Peng, et al., BMC-based temperature-aware SBST for Worst-case Delay fault testing under high temperature, IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (Nov. 2022) 1677–1690,.
[20]
C.H. Wu, K.J. Lee, S.M. Reddy, An efficient diagnosis-aware ATPG procedure to enhance diagnosis resolution and test compaction, IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019) 2105–2118,.
[21]
M. Bushnell, V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI circuits[M], Springer Science & Business Media, 2004.
[22]
K.S. Trivedi, Probability & Statistics with Reliability, Queuing and Computer Science applications[M], John Wiley & Sons, 2008.
[23]
C. Hu, Modern Semiconductor Devices for Integrated circuits[M], Prentice Hall, Upper Saddle River, NJ, 2010, pp. 145–149.
[24]
H.K. Lee, D.S. Ha, HOPE: an efficient parallel fault simulator for synchronous sequential circuits, IEEE Trans. Comput. Aided Des. Integrated Circ. Syst 15 (9) (1996) 1048–1058,.
Digital Library
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Information & Contributors
Information
Published In
Integration, the VLSI Journal Volume 96, Issue C
May 2024
351 pages
ISSN:0167-9260
Issue’s Table of Contents
Elsevier B.V.
Publisher
Elsevier Science Publishers B. V.
Netherlands
Publication History
Published: 02 July 2024
Author Tags
- Circuit complexity
- Test reordering
- Feature size
- Test eigenvalues
Qualifiers
- Research-article
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